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rf signal processor KS1461 1 preliminary introduction the KS1461 receives optical signals from the optical pickup and makes the data-generation rf (radio frequency) signals needed in the system part, and the servo error signal and monitor signals, needed for stable servo control. the modes to which this rf ic can be applied are the cd 1 , 2 , 4 , and 8 modes (wide pll +/- 20%) and the dvd 1 and 2 clv (constant linear velocity) modes. features ? compatible to play back of cds at 1 , 2 , 4 , or 8 , and dvds at 1 and 2 ? can deal with all of cd-r corresponding p/u?s optical signal input without additional circuits ? built-in preamp that correspond to various p/u unit and gain controllable ? built-in agc (automatic gain control) circuit for intensity radiation detection feedback ? rf amp & equalizer for cd 1 , 2 , 4 , 8 and dvd 1 , and 2 compatibility ? astigmatism fe (focus error) amp for cd and dvd built-in ? te (tracking error) amp built-in for 3-beam method of cd ? te (tracking error) amp built-in to the 1-beam dpd (differential phase detector) for dvd ? rf mirror detection circuit built-in for cd and dvd ? rf defect detection circuit built-in for cd and dvd ? fok (focus o.k) signal detection circuit built-in for cd and dvd ? built-in rf envelope signal generator circuit for cd and dvd ? built-in alpc (automatic laser power control) circuit for cd and dvd ? built-in standard voltage generating circuit for analog circuit ? built-in detection circuit for abnormal wave forms ? built-in auto offset compensation circuit ? range of power in operation: 4.5 ~ 5.5v ? 100 pin, tqfp (0.5 mm pitch)
KS1461 rf signal processor 2 ldi-97-p002-r2 98-02-10 preliminary block diagram r f e q u a l i z e r a l p c d 1 b 1 a 1 c 1 d c d 1 d d v d 1 b d v d 1 a d v d 1 c d v d 1 b c d 1 c c d 1 a c d 1 f e m u x t e s e l ( 0 0 h ) a u t o o f s t c t l t e 3 b r f c t & m i r r d p d v c c l d o d v d a b c d n 1 2 1 7 1 4 1 5 1 6 2 5 2 2 7 0 5 5 1 0 0 9 8 9 4 9 2 8 9 8 5 9 1 7 6 8 4 8 7 8 8 8 2 9 3 g c a t b a l ( 0 1 h ) t e o f s t ( 0 4 h ) g a i n _ t e 3 ( 0 2 h ) - + 2 1 1 8 1 9 2 0 f o k t h d f c t _ c p 2 c c 1 d g n d 8 0 7 7 7 8 7 9 8 1 r f r p 7 1 a b c d i e n v 9 0 c d 1 + + + + r f s u m & a g c g a i n _ e q ( 0 2 h ) e n v e l o p e f o k d e f e c t 2 4 a v c c p d v d p d l i m i t r e s a b c d s u b r f m u x 9 7 9 5 9 6 9 9 8 6 v r e f e q 7 4 7 3 7 2 5 2 5 1 c l o c k d a t a v r e f d p d t o d p d b l o c k t o r f e q t u n i n g b l o c k 1 3 2 3 f o f s t l d o c d p d c d 5 3 5 4 d v c c 7 5 b c a f a u l t o u t 5 6 8 3 a g n d s t b d p d g n d m u x b c a i d p d e q 2 d p d e q 1 d f c t 2 t e 3 o f s t a n a l o g v c a m p v r e f a d f c t _ c p 1 v r e f l p _ b g i c c 2 d p d v c a m p t e n t e d f c t 1 f e p l l c t l t e 1 r e s m i r r d p d m u t e o s c f o k b - + f o f s t a b c d s u m + f e o f s t h o l d f e n d f c t t h 2 d f c t t h 1 e n v p e n v b r e s e t b c a o a g c _ d e t r f a g c o a g c l e v e l a g c i e q v c c r f e q o p l l f b c a t h e q f r d p f v z o c t l a g c c r f c t e q g n d c p 1 m i r r i r f r p n c p 2 c b 2 r f r p a g c p a g c b c b 1 m r o f s t e q i n r r e f d l y v r e f g e n e r a t o r r r e f b f r r e f r r e f e q e q v c a m p 5 8 6 0 5 9 5 7 6 5 6 2 6 3 6 1 6 4 6 8 6 7 6 6 6 9 s / i f b l o c k c d 1 s 1 2 d v d 1 d v d 2 l d o n b f l t _ c t l c d r s e l t e s e l a g c h o l d t b a l g a i n _ t e 3 e n v _ s e l d v c t l _ s e l d p d _ m u t e g a i n _ e q g a i n _ f e g a i n _ a b c d t e _ o f s t f e _ o f s t a b c d _ o f s t d e l a y _ c d d e l a y _ a b p d l i m i t g a _ r f s u m h o l d _ c t l g a _ p l l d p g a _ p l l d n b c a b l o c k b c a m u x e q i n - + a g c - h o l d ( 0 0 h ) e n v _ s e l ( 0 2 h ) l d o n b ( 0 0 h ) c o m d p d e q 1 d p d e q 2 c o m d e l a y d e l a y _ a b ( 0 7 h ) d e l a y _ c d ( 0 7 h ) p l l c t l t e o f s t ( 0 4 h ) p d , l p f p d _ l i m i t ( 0 8 h ) d e l a y _ s e l ( 0 0 h ) p l l c t l t b a l ( 0 1 h ) d e l a y _ s e l ( 0 0 h ) p l l c t l f a u l t o u t t e 1 r e s t e 1 _ l i m i t p d l i m i t r e s g a _ p l l d n ( 0 9 h ) g a _ p l l d p ( 0 9 h ) + + e q + + e q c d r s e l ( 0 0 h ) d b a c r f m u x a c d c c d d c d b c d 6 7 8 a d v d c d v d d d v d b d v d 2 3 4 5 1 d d d d m u x 3 d v c t l _ s e l ( 0 2 h ) g c a g c a g a _ r f s u m ( 0 8 h ) h o l d _ c t l ( 0 8 h ) d p d m u t e d p d _ m u t e ( 0 2 h ) s e o f h o l d f l t _ c t l ( 0 0 h ) c a l _ e n d b ( 0 2 h ) c d r s e l ( 0 0 h ) o f s t h o l d g a i n _ f e ( 0 3 h ) o f s t h o l d + + + - c d r s e l ( 0 0 h ) o f s t h o l d s 1 2 g a i n _ a b c d ( 0 0 h ) a b c d _ o f s t ( 0 6 h ) f e _ o f s t ( 0 5 h ) 9 1 0 1 1 a b n o r m a l w a v e f o r m d e t e c t i o n c i r c u i t g c a 3 1 4 2 4 3 4 6 4 4 5 0 2 6 2 7 4 0 4 1 4 7 4 8 3 9 4 5 3 4 2 8 3 2 3 3 2 9 3 0 3 6 3 7 3 8 3 5 4 9 e q g
rf signal processor KS1461 3 preliminary pin description table 1. pin description pin no. pin name i/o description related block related part 1 acd i optical main beam a, ac coupling input terminals for cd of rf block pre amp p/u 2 bcd i optical main beam b, ac coupling input terminals for cd of rf block pre amp p/u 3 ccd i optical main beam c, ac coupling input terminals for cd of rf block pre amp p/u 4 dcd i optical main beam d, ac coupling input terminals for cd of rf block pre amp p/u 5 advd i optical main beam a, ac coupling input terminals for dvd of rf block pre amp p/u 6 bdvd i optical main beam b, ac coupling input terminals for dvd of rf block pre amp p/u 7 cdvd i optical main beam c, ac coupling input terminals for dvd of rf block pre amp p/u 8 ddvd i optical main beam d, ac coupling input terminals for dvd of rf block pre amp p/u 9 rrefbf - rf amp i/o buffer bias resistance connection terminal rf amp - 10 rrefeq - rf eq bias resistance connection terminal rf eq - 11 rref - analog block bias resistance connection terminal analog - 12 vrefeq - cap connection terminal for rf eq center voltage eq vc amp - 13 e i cd optical sub beam e input terminal for servos te 3b p/u 14 f i cd optical sub beam f input terminal for servos te 3b p/u 15 advd1 i optical main beam a input terminal for dvd of servo block servo amp p/u 16 bdvd1 i optical main beam b input terminal for dvd of servo block servo amp p/u 17 cdvd1 i optical main beam c input terminal for dvd of servo block servo amp p/u 18 ddvd1 i optical main beam d input terminal for dvd of servo block servo amp p/u 19 acd1 i optical main beam a input terminal for cd of servo block servo amp p/u 20 bcd1 i optical main beam b input terminal for cd of servo block servo amp p/u 21 ccd1 i optical main beam c input terminal for cd of servo block servo amp p/u 22 dcd1 i optical main beam d input terminal for cd of servo block servo amp p/u 23 avcc p power voltage input terminal for analog part analog - 24 vrefa i/o cap connection terminal for analog part center voltage uses an external block ana vc amp servo 25 fofst - cap connection terminal (open) for focus auto offsets fe amp - 26 ofsthold i on/off terminal for auto offset block. (l: auto offset adjustments, h: serial offset adjustments) ofstctl micom
KS1461 rf signal processor 4 ldi-97-p002-r2 98-02-10 preliminary 27 vreflp_bgi i band gap voltage input block for alpc alpc - 28 ldodvd o optical laser diodes operation voltage output terminal for dvd alpc p/u 29 pddvd i optical laser monitor diode voltage input terminal for dvd alpc p/u 30 ldocd o optical laser diode operating voltage output terminal for cd alpc p/u 31 pdcd i optical laser monitor diode voltage input terminal for cd alpc p/u 32 agnd p power gnd terminal for analog part analog - 33 fe o fe amp output terminal fe amp dssp 34 fen i input terminal for selecting fe amp gain fe amp - 35 ten i input terminal for selecting te amp gain te amp - 36 te o te amp output terminal te amp dssp 37 pdlimtres - bias resistance terminal for pdlimit dpd - 38 abcdn i abcd amp for selecting gain ( - ) input terminal abcd amp - 39 abcd o abcd amp output terminal abcd amp - 40 abcdi i abcd ac coupling input terminal for servo monitor servo monit - 41 envp - cap connection terminal for selecting the rc value of peak hold for detecting rf envelopes rf env - 42 envb - cap connection terminal for selecting the rc value of bottom hold for detecting rf envelopes rf env - 43 env o rf envelope detect output terminal rf env dssp 44 dgnd p power gnd input terminal for digital circuits digital - 45 fokth i focus ok comparating level input terminal fokb - 46 fokb o focus ok comparator output terminal (l: focus ok) fokb dssp 47 dfct_cp1 - connection terminal for rc value of peak hold, for selecting the maximum time for servo signal dfct - 48 dfct_cp2 - connection terminal for rc value of peak hold, for selecting the minimum defect time for pll dfct - 49 cc1 o peak hold output terminal for selecting the minimum defect time for defect dfct - 50 cc2 i peak hold ac coupling input terminal for defect dfct - 51 dvcc p power voltage input terminal for digital circuit digital - 52 dfctth2 - resistance connection terminal for selecting the defect comparat- ing level for pll defect - 53 dfctth1 - resistance connection terminal for selecting the defect comparat- ing level for servo defect - 54 dfct1 o defect output terminal for servo defect dssp 55 dfct2 o defect output terminal for pll defect pll 56 dpdvcc p power voltage input terminal for dpd te dpd - 57 mirr o mirror output terminal mirr dssp 58 bca o bca output terminal bca dsp table 1. pin description pin no. pin name i/o description related block related part
rf signal processor KS1461 5 preliminary 59 te3ofst - cap connection terminal (open) for 3b te offset 3b te amp - 60 dpdeq1 o dpd eq (a+c) output terminal dpd - 61 dpdeq2 o dpd eq (b+d) output terminal dpd - 62 faultout o dpd abnormal wave form output terminal (monitor) dpd - 63 dpdmute i dpd te mute control terminal (h: mute) dpd micom 64 pllctl i dpd te pll variable input terminal dpd servo 65 te1res i dpd te pll variable bias resistance dpd - 66 dpdgnd p power gnd input terminal for dpd te dpd - 67 vrefdpd o cap connection terminal for dpd te center voltage dpd vc amp - 68 rrefdly - bias resistance connection terminal for delay block delay block - 69 data i data input terminal serial interface micom 70 clock i clock input terminal serial interface micom 71 stb i data enable input terminal serial interface micom 72 osc input terminal for rc value of osc, for auto offset block auto ofstctl - 73 reset i reset input terminal (l: reset) for auto offset block auto ofstctl micom 74 bcai i bca filter1 bca - 75 bcao o bca filter2 bca - 76 rfct o rf ripple center voltage output terminal for mirror mirror dssp 77 cb2 - cap connection terminal of rc value of bottom hold, for rfct generation mirror - 78 cp2 - cap connection terminal of rc value of peak hold, for rfct gen- eration mirror - 79 rfrp o rf ripple amp output terminal for mirror mirror dssp 80 rfrpn i input terminal for selecting rfrp amp gain mirror - 81 mrofst i rf ripple offset control terminal for mirror mrror - 82 cb1 - rc connection terminal of rc value of bottom hold, for rfrp generation mrror - 83 cp1 - rc connection terminal of rc value of peak hold, for rfrp gen- eration mrror - 84 mirri i input terminal for mirr signal generation mrror - 85 eqvcc p power voltage input signal for rf eq rf eq - 86 rfeq0 0 rf eq output terminal rf eq pll 87 bcath i bca comparating level control terminal bca dsp 88 eqin i rfagco input terminal for rf eq rfeq,rfenv dssp 89 rfagco o rf agc amp output terminal rf agc - 90 agcc - cap connection terminal for time constant of agc rf agc - 91 agci i agc voltage input terminal while in agc hold rf agc - table 1. pin description pin no. pin name i/o description related block related part
KS1461 rf signal processor 6 ldi-97-p002-r2 98-02-10 preliminary 92 eqgnd p power gnd input terminal for rf eq rf eq - 93 agclevel i agc level control voltage input terminal (3.5 v) while in agc hold off rf agc - 94 agcb - rc connection terminal for rc value of bottom hold, for rf agc rf agc - 95 agcp - rc connection terminal for rc value of peak hold, for rf agc rf agc - 96 rdpf - bias resistance connection terminal for selecting rf eq frequency rf eq - 97 eqg i rf eq boost gain control voltage input terminal rf eq dssp 98 eqf i rf eq peak frequency control voltage input terminal rf eq dssp 99 pllf i wide-band pll compatible rf eq peak frequency control termi- nal rf eq dssp 100 vzoctl i rf eq zero control terminal rf eq dssp table 1. pin description pin no. pin name i/o description related block related part
rf signal processor KS1461 7 preliminary electrical characteristics vcc = 5v, gnd = 0v, vc = 2.5v ta = 25 c, vc is center of standard output voltage. table 2. electrical characteristics no item symbol input measurement point min. typ. max. unit circuit current 1 power current icc no signal 150 170 190 ma rf sum & agc amp 2 rf sum amp voltage gain vrfsum1 dvd: 1mhz (a-d) dvd: 300mvpp rfagco (agci=1.5v, agchold=h) 0.8 1 1.2 vpp 3 vrfsum2 cd: 0.2mhz (a-d) cd: 150mvpp 4 rf sum amp unit gain band- width frfsum1 dvd: frequency sweep (a-d) dvd: 300mvpp + 120mvdc 20 - - mhz 5 frfsum2 cd: frequency sweep (a-d) cd: 150mvpp + 120mvdc 20 - - mhz 6 agc voltage gain gagc1 each mode standard input agcin: 2.5v rfagco (standard gain comparison) 6.0 - - db 7 gagc2 each mode standard input agcin: 0.5v - - -6.0 8 agc level vagc each mode standard input agclevel = 3.5v rfagco 0.8 1 1.2 vpp abcd sum amp 9 abcd sum amp voltage gain vsum1 dvd: 100khz (a1~d1) dvd: 300mvpp + 150mvdc abcd (agci =1.5v, agchold=h) 0.8 1 1.2 vpp 10 vsum2 cd: 100khz (a1~d1) cd: 150mvpp + 120mvdc 11 rf sum amp -3db gain bandwidth fsum1 dvd: frequency sweep (a1~d1) dvd: 300mvpp + 150mvdc abcd 4 - - mhz 12 fsum2 cd: frequency sweep (a1~d1) cd: 150mvpp + 120mvdc 4 - - mhz rf equalizer 13 eq standard output vrfeq rfagco = 1vpp rfeqo 1.9 2.0 2.1 vpp 14 eq peak frequency fpdvd1 a ~ d: standard input swept sine rfeqo - 6.4 - mhz 15 fpdvd2 - 12.8 - 16 fpcd1 - 1.3 - 17 fpcd2 - 2.6 - 18 fpcd4 - 5.2 - 19 fpcd8 - 10.4 - 20 group delay variation d tdvd1 a ~ d: standard input swept sine rfeqo - - 3 ns 21 d tdvd2 - - 1.5 22 d tcd1 - - 20 23 d tcd2 - - 5 24 d tcd4 - - 2.5 25 d tcd8 - - 1.5
KS1461 rf signal processor 8 ldi-97-p002-r2 98-02-10 preliminary 26 maximum gain frequency (f peak ) range fpeak1 a ~ d: standard input swept sine, eqg: vc, eqf: 3.5v rfeqo f peak +18 f peak +20 f peak +22 % 27 fpeak2 a ~ d: standard input swept sine, eqg: vc, eqf: 2.5v f peak -10 f peak +0 f peak +10 28 fpeak3 a ~ d: standard input swept sine, eqg: vc, eqf: 1.5v f peak -22 f peak -20 f peak -18 29 maximum gain (g peak ) range gpeak1 a ~ d: standard input swept sine, pll, eqf: vc, eqg: 1.5v rfeqo 2.1 3.0 3.8 db 30 gpeak2 a ~ d: standard input swept sine, pll, eqf: vc, eqg: 2.5v -0.9 0.0 0.8 31 gpeak3 a ~ d: standard input swept sine, pll, eqf: vc, eqg: 3.5v -3.8 -3.0 -2.1 32 frequency characteristics range corre- spond to wide pll fpll1 a ~ d: standard input swept sine, eqf, eqg: vc, pll: 3.75v rfeqo f peak +18 f peak +20 f peak +22 % 33 fpll2 a ~ d: standard input swept sine, eqf, eqg: vc, pll: 2.5v f peak -10 f peak f peak +10 34 fpll3 a ~ d:standard input swept sine, eqf, eqg: vc, pll: 1.25v f peak -22 f peak -20 f peak -18 35 gain character- istics range correspond to wide pll gpll a ~ d: standard input swept sine, eqf,eqg: vc, pll: 3.5v, 2.5v, 1.5v rfeqo g peak -0.8 g peak g peak +0.8 db focus error amp 36 voltage gain vfedvd1 (a1,c1) dvd: 1khz 300mvpp sine + vc (b,d) dvd: vc fe 0.9 1 1.1 vpp 37 vfedvd2 (b1,d1) dvd: 1khz 300mvpp sine + vc (a,c) dvd: vc 38 vfecd1 (a1,c1) cd: 1khz 150mvpp sine + vc (b,d) cd: vc 39 vfecd2 (b1,d1) cd: 1khz 150mvpp sine + vc (a,c) cd: vc 40 output voltage h vfeh b1 = vc + 2.0vdc, a1, c1, d1 = vc fe +2.0 +2.1 - v 41 output voltage l vfel b1 = vc - 2.0vdc, a1, c1, d1 = vc - -2.1 -2.0 42 bandwidth (-3db freq.) ffedvd (a1, c1) dvd: 300mvpp swept sine + vc (b1, d1) dvd: vc fe 50k 60k 70k hz 43 ffecd (a1, c1) cd: 150mvpp swept sine + vc (b1, d1) cd: vc 50k 60k 70k hz 44 offset voltage vosfe (a1 ~ d1) cd, dvd: vc fe -300 0 300 mv tracking error amp (1 - beam) 45 dpd eq stan- dard gain vote1 (a~d) dvd: 281mvpp 200khz sine + vc gain_te1 = 5 db dpdmon1 dpdmon2 1.8 2.0 2.2 v 46 variable range of dpd input amp gain vogte1 (a~d) dvd: 100mvpp 200khz sine + vc gain_te1 = 20 db dpdmon1 dpdmon2 1.8 2.0 2.2 v 47 vogte2 (a~d) dvd: 1000mvpp 200khz sine + vc gain_te1= 2.5 db 2.39 2.66 2.93 table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit
rf signal processor KS1461 9 preliminary 48 output voltage correspond to phase differ- ence. vph1 (a~d) dvd: 250mvpp 21mhz sine + vc (a,c)dvd is 45 ahead of (b,d)dvd te -1.0 v 49 vph2 (a~d) dvd: 250mvpp 21mhz sine + vc (a,c)dvd and (b,d)dvd?s phase difference = 0 te 0 50 vph3 (a~d) dvd: 250mvpp 21mhz sine + vc (a,c)dvd is 45 behind of (b,d)dvd te +1.0 51 variable range of dpd fre- quency charac- teristics fte1 (a~d) dvd: 250mvpp sweeping sine zero frequency when dpdeq register is changed dpdmon1 dpdmon2 0.7 - 2.8 mhz 52 fte2 (a~d) dvd: 250mvpp sweeping sine 1st pole frequency when dpdeq register is changed 7 - 28 53 fte3 (a~d) dvd: 250mvpp sweeping sine 2nd pole frequency when dpdeq register is changed 10 - 40 54 depth control adjustment range1 (dvd 1x pll = 2.5 v dmax=80 ns) tdepc1 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = 0 (1/16*dmax) = 5 ns, delay_cd = 7 (1/2*dmax) = 40 ns te -0.88 -0.73 -0.59 v 55 tdepc2 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = f (dmax) = 80 ns, delay_cd = 7 (1/2*dmax) = 40 ns 0.67 0.84 1.00 56 tdepc3 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = 7 (1/2*dmax) = 40 ns, delay_cd = 0 (1/16*dmax) = 5 ns 0.59 0.73 0.88 57 tdepc4 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = 7 (1/2*dmax) = 40 ns, delay_cd = f (dmax) = 80 ns -1.00 -0.84 -0.67 58 depth control adjustment range2 (dvd 1x pll = 3.75 v dmax=53.3 ns) tdepc5 (a,b,c,d)dvd: 250mvpp 3.924mhz sine + vc delay_ab = 0 (1/16*dmax) = 3.33 ns, delay_cd = 7 (1/2*dmax) = 26.65 ns te -0.88 -0.73 -0.59 v 59 tdepc6 (a,b,c,d)dvd: 250mvpp 3.924mhz sine + vc delay_ab = f (dmax) = 53.3 ns, delay_cd = 7 (1/2*dmax) = 26.65 ns 0.67 0.84 1.00 60 tdepc7 (a,b,c,d)dvd: 250mvpp 3.924mhz sine + vc delay_ab = 7 (1/2*dmax) = 26.65 ns, delay_cd = 0 (1/16*dmax) = 3.33 ns 0.59 0.73 0.88 61 tdepc8 (a,b,c,d)dvd: 250mvpp 3.924mhz sine + vc delay_ab = 7 (1/2*dmax) = 26.65 ns, delay_cd = f (dmax) = 53.3 ns -1.00 -0.84 -0.67 62 depth control adjustment range3 (dvd 1x pll = 1.25 v dmax=160 ns) tdepc9 (a,b,c,d)dvd: 250mvpp 1.308mhz sine + vc delay_ab = 0 (1/16*dmax) = 10 ns, delay_cd = 7 (1/2*dmax) = 80 ns te -0.88 -0.73 -0.59 v 63 tdepc10 (a,b,c,d)dvd: 250mvpp 1.308mhz sine + vc delay_ab = f (dmax) = 160 ns, delay_cd = 7 (1/2*dmax) = 80 ns 0.67 0.84 1.00 64 tdepc11 (a,b,c,d)dvd: 250mvpp 1.308mhz sine + vc delay_ab = 7 (1/2*dmax) = 80 ns, delay_cd = 0 (1/16*dmax) = 10 ns 0.59 0.73 0.88 65 tdepc12 (a,b,c,d)dvd: 250mvpp 1.308mhz sine + vc delay_ab = 7 (1/2*dmax) = 80 ns, delay_cd = f (dmax) = 160 ns -1.00 -0.84 -0.67 table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit
KS1461 rf signal processor 10 ldi-97-p002-r2 98-02-10 preliminary 66 depth control adjustment range4 (dvd 2x pll = 2.5 v dmax=40 ns) tdepc13 (a,b,c,d)dvd: 250mvpp 5.232mhz sine + vc delay_ab = 0 (1/16*dmax) = 2.5 ns, delay_cd = 7 (1/2*dmax) = 20 ns te -0.88 -0.73 -0.59 v 67 tdepc14 (a,b,c,d)dvd: 250mvpp 5.232mhz sine + vc delay_ab = f (dmax) = 40 ns, delay_cd = 7 (1/2*dmax) = 20 ns 0.67 0.84 1.00 68 tdepc15 (a,b,c,d)dvd: 250mvpp 5.232mhz sine + vc delay_ab = 7 (1/2*dmax) = 20 ns, delay_cd = 0 (1/16*dmax) = 2.5 ns 0.59 0.73 0.88 69 tdepc16 (a,b,c,d)dvd: 250mvpp 5.232mhz sine + vc delay_ab = 7 (1/2*dmax) = 20 ns, delay_cd = f (dmax) = 40 ns -1.00 -0.84 -0.67 70 depth control adjustment range5 (dvd 2x pll = 3.75v dmax=26.67ns) tdepc17 (a,b,c,d)dvd: 250mvpp 7.848mhz sine + vc delay_ab = 0 (1/16*dmax) = 1.67 ns, delay_cd = 7 (1/2*dmax) = 13.335 ns te -0.88 -0.73 -0.59 v 71 tdepc18 (a,b,c,d)dvd: 250mvpp 7.848mhz sine + vc delay_ab = f (dmax) = 26.67 ns, delay_cd = 7 (1/2*dmax) = 13.335 ns 0.67 0.84 1.00 72 tdepc19 (a,b,c,d)dvd: 250mvpp 7.848mhz sine + vc delay_ab = 7 (1/2*dmax) = 13.335 ns, delay_cd = 0 (1/16*dmax) = 1.67 ns 0.59 0.73 0.88 73 tdepc20 (a,b,c,d)dvd: 250mvpp 7.848mhz sine + vc delay_ab = 7 (1/2*dmax) = 13.335 ns, delay_cd = f (dmax) = 26.67 ns -1.00 -0.84 -0.67 74 depth control adjustment range6 (dvd 2x pll = 1.25 v dmax=80 ns) tdepc21 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = 0 (1/16*dmax) = 5 ns, delay_cd = 7 (1/2*dmax) = 40 ns te -0.88 -0.73 -0.59 v 75 tdepc22 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = f (dmax) = 80 ns, delay_cd = 7 (1/2*dmax) = 40 ns 0.67 0.84 1.00 76 tdepc23 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = 7 (1/2*dmax) = 40 ns, delay_cd = 0 (1/16*dmax) = 5 ns 0.59 0.73 0.88 77 tdepc24 (a,b,c,d)dvd: 250mvpp 2.616mhz sine + vc delay_ab = 7 (1/2*dmax) = 40 ns, delay_cd = f (dmax) = 80 ns -1.00 -0.84 -0.67 78 accuracy according to delay step (dvd speed & pll voltage is variable) dmax = maxi- mum delay at each mode vdlyacc1 (a,b,c,d) dvd: 250mvpp + vc, variable frequency according to speed & pll voltage delay_ab = step variable delay_cd = 7 (1/2*dmax) dpdmon1 dpdmon2 83.7 104.6 125.5 mv 79 vdlyacc2 (a,b,c,d) dvd: 250mvpp + vc variable frequency according to speed & pll voltage delay_ab = 7 (1/2*dmax) delay_cd = step variable 83.7 104.6 125.5 80 tracking bal- ance adjust- ment range1 vbalc1 (a,c) dvd: 250 mvpp 2.616mhz sine + vc (b,d) dvd: 250mvpp 2.616mhz sine +vc tbal: step variable dvd 1x, pll = 2.5v te -1.2 1.2 v table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit
rf signal processor KS1461 11 preliminary 81 tracking bal- ance adjust- ment range2 vbalc2 (a,c) dvd: 250 mvpp 3.924mhz sine + vc (b,d dvd: 250mvpp 3.924mhz sine +vc tbal: step variable dvd 1x, pll = 3.75v te -1.2 1.2 v 82 tracking bal- ance adjust- ment range3 vbalc3 (a,c) dvd: 250 mvpp 1.308mhz sine + vc (b,d) dvd: 250mvpp 1.308mhz sine +vc tbal: step variable dvd 1x, pll = 1.25v te -1.2 1.2 v 83 tracking bal- ance adjust- ment range4 vbalc4 (a,c) dvd: 250 mvpp 5.232mhz sine + vc (b,d) dvd: 250mvpp 5.232mhz sine +vc tbal: step variable dvd 2x, pll = 2.5v te -1.2 1.2 v 84 tracking bal- ance adjust- ment range5 vbalc5 (a,c) dvd: 250 mvpp 7.848mhz sine + vc (b,d) dvd: 250mvpp 7.848mhz sine +vc tbal: step variable dvd 2x, pll = 3.75v te -1.2 1.2 v 85 tracking bal- ance adjust- ment range6 vbalc6 (a,c )dvd: 250 mvpp 2.616mhz sine + vc (b,d) dvd: 250mvpp 2.616mhz sine +vc tbal: step variable dvd 2x, pll = 1.25v te -1.2 1.2 v 86 tracking balance adjustment accuracy vbalacc (a,c )dvd, (b,d) dvd: standard input according to each speed & pll voltage tbal: step variable, dvd speed & pll voltage is variable. te 10 mv 87 phase compar- ator limit1 vphlim1 (a,c) dvd: input1, fin1=2mhz, (b,d) dvd: input2, pd_limit=90ns te 1.296 1.44 1.584 v 88 vphlim2 (a,c) dvd: input1, (b,d) dvd: input2, fin1 = 2mhz pd_limit = 90ns te -1.584 -1.44 -1.296 89 phase compar- ator limit2 vphlim3 (a,c) dvd: input1, fin1=2mhz (b,d) dvd: input2, pd_limit = 60ns te 0.864 0.96 1.056 v 90 vphlim4 (a,c )dvd: input1, (b,d) dvd: input2, fin1=2mhz pd_limit = 60ns te -1.056 -0.96 -0.864 91 phase compar- ator limit3 vphlim5 (a,c) dvd: input1, fin1 = 2mhz (b,d) dvd: input2, pd_limit = 30ns te 0.432 0.48 0.528 v 92 vphlim6 (a,c) dvd: input1, (b,d) dvd: input2, fin1 = 2mhz pd_limit = 30ns -0.528 -0.48 -0.432 93 abnormal waveform detecting cir- cuit 1 (dvd 1x, pll = 2.5v) tflt1 (a,c) dvd: input1, fin1 = 200khz (b,d) dvd: input2 measuring the time from falling edge where only (b,d) dvd exists, to when faulto goes ?high? (b,d) dvd faulto -10% 611.6 +10% ns table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit
KS1461 rf signal processor 12 ldi-97-p002-r2 98-02-10 preliminary 94 abnormal waveform detecting cir- cuit 2 (dvd 1x, pll = 3.75v) tflt2 (a,c) dvd: input1,fin1 = 300khz (b,d) dvd: input2 measuring the time from falling edge where only (b,d) dvd exists, to when faulto goes ?high? (b,d) dvd faulto -10% 407.7 +10% ns 95 abnormal waveform detecting cir- cuit 3 (dvd 1x, pll = 1.25v) tflt3 (a,c) dvd: input1, fin1 = 100khz (b,d) dvd: input2 measuring the time from falling edge where only (b,d) dvd exists, to when faulto goes ?high? (b,d) dvd faulto -10% 1223.2 +10% ns 96 abnormal waveform detecting cir- cuit 4 (dvd 2x, pll = 2.5v) tflt4 (a,c) dvd: input1, fin1 = 400khz (b,d) dvd: input2 measuring the time from falling edge where only (b,d) dvd exists, to when faulto goes ?high? (b,d) dvd faulto -10% 305.8 +10% ns 97 abnormal waveform detecting cir- cuit 5 (dvd 2x, pll = 3.75v) tflt5 (a,c) dvd: input1, fin1 = 600khz (b,d) dvd: input2 measuring the time from falling edge where only (b,d) dvd exists, to when faulto goes ?high? (b,d) dvd faulto -10% 203.9 +10% ns 98 abnormal waveform detecting cir- cuit 6 (dvd 2x, pll = 1.25v) tflt6 (a,c) dvd: input1, fin1 = 200khz (b,d) dvd: input2 measuring the time from falling edge where only (b,d) dvd exists, to when faulto goes ?high? (b,d) dvd faulto -10% 611.6 +10% ns 99 offset voltage voste1 dpdmute = h te -100 0 100 mv 100 phase compar- ator input rise & fall time tphtt all comparators must have a rise & fall time of at least 4 ns/v. - - - 4 ns/v tracking error amp (3 - beam) 101 voltage gain vte31 e: 1khz 120mvpp sine +vc, f: vc, tbal=80h te 0.9 1 1.1 vpp 102 vte32 f: 1khz 120mvpp sine +vc, e: vc, tbal=80h te 103 output voltage h vte3h e: -0.7v, f: vc te +2.0 +2.1 - v 104 output voltage l vte3i e: +0.7v, f: vc te - -2.1 -2.0 105 bandwidth (-3db freq.) fte3 e: 120mvpp swept sine +vc f: vc te 50k 60k 70k hz 106 tracking bal- ance range gte31 tbal = 00h f: 1khz 120mvpp sine +vc te +6 - - db 107 offset voltage gte32 tbal = ffh f: 1khz 120mvpp sine +vc - - -6 db 108 offset voltage voste3 e, f: vc te -300 0 300 mv table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit
rf signal processor KS1461 13 preliminary 109 tracking offset range voste31 e, f: vc, vofst_te: 3.5v te 400 500 600 mv 110 voste31 e, f: vc, vofst_te: 1.5v -600 -500 -400 mirror circuit 111 output voltage h vmirh rfagci: 2.0vpp sine 10khz mirr vcc- 0.5 - - v 112 output voltage l vmirl - - vee +0.4 113 mirr hold fre- quency fhold1 rfagci: 2.0vpp f carrier = 5mhz 35% am modulation mirr - 400 600 hz 114 fhold2 rfagci: 2.0vpp f carrier = 5mhz 70% am modulation - 400 600 115 bottom hold frequency fhold1 rfagci: 2.0vpp f carrier = 5mhz 35% am modulation mirr - 550 900 hz 116 fhold2 rfagci: 2.0vpp f carrier = 5mhz 70% am modulation - 550 900 117 maximum oper- ation frequency fmir1 rfagci: 2.0vpp f carrier = 5mhz 35% am modulation mirr 150k - - vpp 118 fmir2 rfagci: 2.0vpp f carrier = 5mhz 70% am modulation 150k - - 119 minimum input operation volt- age vmirin1 rfagci: voltage sweep sine 10khz mirr - 0.1 0.2 vpp 120 maximum input operation volt- age vmirin2 1.8 - - defect circuit 121 output voltage h vdefh (a1~d1) dvd: 300mvpp + 150mvdc frequency 1khz dfct v cc -0.5 - - v 122 output voltage l vdefl - - vee +0.4 123 minimum oper- ation frequency vdef1 (a1~d1) dvd: 300mvpp + 150mvdc swept sine dfct - - 1.0 khz 124 minimum oper- ation frequency fdef2 5.0 - - 125 minimum input operation volt- age vdefin1 abcdi: 1vpp pulse 5khz symmetry 95% dfct - - 0.5 vpp 126 maximum input operation volt- age vdefin2 1.8 - - fok detect circuit 127 output voltage h vfokh (a1 ~ d1) dvd: 300mvpp (a1 ~ d1) cd: 150mvpp 1khz sine wave fokb v cc -0.5 - - v 128 output voltage l vfokl - - vee +0.4 129 threshold volt- age vfokth dc voltage fokb -0.43 -0.39 -0.35 v table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit
KS1461 rf signal processor 14 ldi-97-p002-r2 98-02-10 preliminary 130 maximum oper- ation frequency ffok (a1 ~ d1) dvd: 300mvpp (a1 ~ d1) cd: 150mvpp swept sine fokb 45k hz rf envelope amp 131 output voltage venv abcdi: 1vpp rfenv 2.45 2.5 2.55 v 132 envelope out- put frequency bandwidth fenv 30hz am modulated signal & 500khz carrier rfenv 3k hz alpc circuit 133 output voltage h valpch (pd) cd, dvd: +600mv (ldo) cd, dvd 2.0 v 134 output voltage l valpcl (pd) cd, dvd: +0mv (ldo) cd, dvd -2.0 135 voltage gain galpc (pd) cd, dvd: +200mvdc + 10mvpp (ldo) cd, dvd 90 100 110 v/v 136 output voltage 1 valpc (pd) cd, dvd: +200mv (ldo) cd,dvd vd - 0.25 vc vc + 0.25 v table 2. electrical characteristics (continued) no item symbol input measurement point min. typ. max. unit i n p u t 2 i n p u t 1 f r e q u e n c y = f i n 1 * 2 , d u t y = 5 0 % f r e q u e n c y = f i n 1 , d u t y = 2 5 % 2 5 0 m v p p 2 5 0 m v p p
rf signal processor KS1461 15 preliminary serial interface serial interface is the part that deals with the following: disc type, speed, agc, and the on/off control of the laser diode. the timing chart of the serial interface is as follows. figure 1. serial port data transfer format u address: 00h - d7: signal for controlling agc function 1: agc off (hold) 0: agc on - d6: tracking error select 1: te3 0: dpd - d5: alpc, mux (rf & sub), fe, abcd sum amp gain select 1: ldocd, pdcd, (a~d)cd, (a~d)cd1, fe(cd), abcdsum(cd) select 0: ldodvd, pddvd, (a~d)dvd, (a~d)dvdi, fe(dvd), abcdsum(dvd) select - d4: abnormal wave select 1: flt hold 0: flt on - d3: laser on/off control terminal 1: laser off 0: laser on - d2 ~ d0: speed select (refer to table on next page) data d7 d6 d5 d4 d3 d2 d1 d0 function agc- hold tesel cdrsel flt_ctl ldonb speed select initial value 0 0 0 0 0 0 0 0 stb data clock address, 8-bit data, 8-bit - clock: clock synchronized with the data transmitted from micom - data: address and data transmitted from micom - stb: signal to show that data is enabled a7 a0 d7 d0
KS1461 rf signal processor 16 ldi-97-p002-r2 98-02-10 preliminary u address 01h: tbal - balance adjustment (tbal) is 0db when address is 80h (excluding tbal dpd mode). - when the address is 00h, tbal is 4db, and when the address is ffh, tbal is -4db (excluding tbal dpd mode). - tbal dpd: controls the voltage of the vcps terminal. like offset, is at minimum value at 00h, and maximum value at ffh. 2.5v output is produced at 80h. u address 02h: gain_te3, gain_teout, gain_eq, gain_te1in adjustment - d3: input abcdi when 0, eqin when 1. - d4: input dpd tracking error ((a+c)-(b+d)) when 0, pit depth deciding signal ((a+b) - (c+d)) when 1. - d5: dpd mute ?off? when 0, ?on? when 1 - d6: 0db when 0, +8db when 1. (rf sum block) u address 03h: gain_fe, gain_abcd adjustment select d2 d1 d0 mode speed 0 x 0 dvd 1x 0 x 1 2x 1 0 0 cd 1x 1 0 1 2x 1 1 0 4x 1 1 1 8x address data 01h tbal data d7 d6 d5 d4 d3 d2 d1 d0 function gain_ eq dpd_ mute dvctl_ sel env_ sel gain_te3 initial value 0 0 0 0 0 0 0 data d7 d6 d5 d4 d3 d2 d1 d0 function x x gain_abcd gain_fe initial value 0 0 0 0 0 0 0
rf signal processor KS1461 17 preliminary u address 03h (gain_fe, gain_abcd), address 02h (gain_te3) gain select u address 04h ~ 06h: various offset adjustment data - offset is at minimum value at 00h, and at maximum value at ffh. 2.5v output is produced at 80h. u address 07h: delay_ab, delay_cd (delay control voltage) - delay_ab (d4 --d7):selects amount of delay for pit depth correction delay a,b - delay_cd (d0 -- d3): selects amount of delay for pit depth correction delay c,d u address 08h: dpd pd_ limit, ga_rfsum, hold_ctl select data gain 0h 0db (minimum value) ~ ~ 7h 8db (maximum value) address data 04h te (1,3) offset 05h fe offset 06h abcd sum offset data d7 d6 d5 d4 d3 d2 d1 d0 function delay_ab delay_cd initial value 0 0 0 0 0 0 0 0 d7 d6 d5 d4 delay 0 0 0 0 dmax *1/16 ~ ~ ~ ~ ~ 1 1 1 1 dmax data d7 d6 d5 d4 d3 d2 d1 d0 function hold_ ctl ga_rfsum pd_limit initial value 0 0 0 0 0 0 0 0
KS1461 rf signal processor 18 ldi-97-p002-r2 98-02-10 preliminary - pd_limit (d0--d3): output range limit of dpd phase detector - ga_rfsum (d4--d6): gain select for dpd te input block - hold_ctl (d7): select terminal between the previous abnormal waveform circuit and the new circuit, the latter functions is the default operation. u address 09h: - ga_plldn (d3 - d5): delay negative sensitivity select following pll - ga_plldp (d0 - d2): delay positive sensitivity select following pll d3 d2 d1 d0 range limit 0 0 0 0 160 ns ~ ~ ~ ~ ~ 1 1 1 1 10 ns d6 d5 d4 mode (rfagco value compared to input value) 0 0 0 2.5 db ~ ~ ~ ~ 1 1 1 20 db data d7 d6 d5 d4 d3 d2 d1 d0 function ga_plldn ga_plldp initial value 0 0 0 0 0 0 0 0 d5 d4 d3 mode (standard input comparison value) 0 0 0 0 db ~ ~ ~ ~ 1 1 1 8 db d2 d1 d0 mode (standard input comparison value) 0 0 0 0 db ~ ~ ~ ~ 1 1 1 8 db
rf signal processor KS1461 19 preliminary test circuit pin100 pin99 pin98 pin97 pin96 pin95 pin94 pin93 pin92 pin91 pin90 pin89 pin88 pin87 pin86 pin85 pin84 pin83 pin82 pin81 p i n 2 p i n 5 3 p i n 5 9 p i n 5 5 pin79 p i n 6 0 p i n 7 0 p i n 6 1 p i n 6 2 p i n 6 3 p i n 6 4 p i n 6 5 p i n 6 6 p i n 6 7 p i n 6 8 p i n 6 9 p i n 7 1 p i n 7 2 p i n 7 3 p i n 7 4 p i n 7 5 pin76 pin77 pin78 pin80 p i n 5 8 p i n 5 7 p i n 5 6 p i n 5 4 p i n 5 2 p i n 5 1 pin50 pin49 pin48 pin47 pin46 pin45 pin44 pin43 pin42 pin41 pin40 pin39 pin38 pin37 pin36 pin35 pin34 pin33 pin32 pin31 pin30 pin29 pin28 pin27 pin26 p i n 2 5 p i n 2 4 p i n 2 3 p i n 2 2 p i n 2 1 p i n 1 p i n 3 p i n 4 p i n 5 p i n 6 p i n 7 p i n 8 p i n 9 p i n 1 0 p i n 1 1 p i n 1 2 p i n 1 3 p i n 1 4 p i n 1 5 p i n 1 6 p i n 1 7 p i n 1 8 p i n 1 9 p i n 2 0 f e bi1461x i335 5 0 k 5 0 k h l 1 0 0 p on h l 100p h l 100p beeds 1 0 0 k 1 0 0 k b e e d s b e e d s 100k b e e d s 100p h l 100p h l on 0 . 1 u 0 . 1 u data clk stb gnd 2 0 p 3 0 k o n h l 100p h l 100p h l 100p h l 100p h l 100p 1 0 0 p h l 100p h l o n 100p h l on on on 0.1u 4 0 k 1 0 0 p 1 2 k 1 2 k 100k 0.1u 100k 0.1u 100k 0.01u 5k 10u 100k 100k 0.01u 100k 0.01u 20k 20k 12k 20k 20k 20k 20k 1 0 u 1 0 u 1 0 u 0.1u 20k 20k 0.1u 100k 0.1u 100k 0.1u 100k 330p 100k 100k 100k 0.01u 0 . 1 u 4 0 k 0.01u 100k 1 0 p 1 2 k 1 2 k 1 2 k 0.01u bnc3 bnc4 bnc1 bnc2 bcath fokth dvd cd alpcin ofsthold vref_bg ef+abcd f+bd e+ac abcd b+d a+c vzoctl pllf eqf eqg agclvl agci r e s e t p l l c t l mrofst d p d m u t e vss vcc
rf signal processor KS1461 20 preliminary pakage dimension 100-tqfp-1414

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